1. Field of the Invention
The present invention relates to a data reproducing device used in, for instance a hard disk drive, and having, in particular a read channel of a PRML system.
2. Description of the Related Art
Conventionally, as shown in FIG. 19, a hard disk drive (HDD) is provided with a read channel 200 for performing reproducing processing, by which recorded data is reproduced by inputting a read signal read from a disk 100 by means of a head 101. Recorded data is write data of, for instance a NRZ (non return to zero) code output from a disk controller (HDC) 2 when this is recorded in the disk 100. During a data recording operation, the recorded data (NRZ data) is modulated to a write signal of a RLL (run length limited) code by means of a ENDEC (encoder and decoder) and sent to the head 101.
A number of tracks TR are constructed in the disk 100 and each track TR is provided with a plurality of data sectors arrayed in a circumferential direction. In a CDR (constant density recording) system, as shown in FIG. 19, a plurality of data sectors DS0 and DS1 are disposed between servo areas SA0 and SA1. The number of data sectors per track is different from zone to zone including a plurality of tracks. A zone is equivalent to a group when a number of tracks TR are divided into a plurality of groups in a radial direction of a disk. By means of such a data format structure, it is possible to make data recording densities almost uniform among the zones. In the servo areas SA0 and SA1, servo data are recorded so as to position the head 101 in an access target position (target track).
The read channel is, as shown in FIG. 19, for reproducing a read signal RS output from a head amplifier 1 and outputting reproduced recorded data NRZ data to the HDC2 together with a read clock (synchronous clock signal) RC output from a read PLL (phase locked loop) 12. The head amplifier 1 is for amplifying a read signal read by means of the head 101.
With an increase in a HDD storage capacity in recent years, there has been presented, as a technique for realizing a high recording density of a disk, a read channel employing a signal processing technique called a PRML (Partial Response Maximum Likelihood) system.
The read channel of this PRML system is a circuit including a PR (Partial Response) equalizer (PRE) 6 and a viterbi decoder 9 of a maximum likelihood decoding system for selecting a most reliable string for reproduction of precorrelated data strings. The PRML system is advantageous compared with a conventional peak detecting system in that it is excellent in a S/N characteristic and an error rate is extremely low.
In addition to the above-described circuit elements, the read channel is provided with a variable gain amplifier (VGA) 3 gain-controlled by means of an automatic gain controller (AGC) 8, a low-pass filter (LPF) 4, a AID converter 5, a synch byte detection circuit 7, a ENDEC (including a NRZ decoder) 10, a write clock generation circuit 11 and a clock switching circuit 13.
The VGA 3 holds a level of a read signal RS from the head amplifier 1 constant. The LPF 4 eliminates high-pass noises from the read signal RS. The AID converter 5 converts the analog read signal RS into digital data.
The synch byte detection circuit 7 searches, as shown in FIG. 20A, a synch byte area (SB) of each data sector constituting a track format on a disk and outputs a detected signal SBD thereof to the HDC 2. Here, a format shown in FIG. 20A means not a track format on a disk but a format of the read signal RS read by means of the head 101. Each data sector is provided with a data area (DATA) in which user data (recorded data) is recorded. In the CDR system, the numbers of data sectors respectively arrayed between the servo areas are not the same. As described later, there is a format in which a data sector is divided sandwiching the servo area (data split).
In the synch byte area (SB), there is recorded information for acquiring synchronization when NRZ data is demodulated by byte unit by means of the decoder 10. A VFO area (PLL synch area) is for acquiring synchronization of a data identifying window and preamble data consisting of a synchronous pattern of a predetermined frequency. That is, the read PLL 12 executes an operation of phase acquisition within the range of the preamble data recorded in the VFO area. In FIG. 20D, a time Tac of the read PLL 12 indicates a phase acquisition time thereof.
The read channel usually starts data reproducing processing in synchronization with a start timing signal called a read gate RG supplied from the HDC 2. That is, as shown in FIG. 20B, data reproducing processing is started when the read gate RG is switched ON (logical level "H") and stopped when this is switched OFF (logical level "L").
In the HDD, a sector signal (pulse signal) SP for detecting a lead portion of each data sector is generated. The sector signal SP is generated by means of a main controller composed of a logic circuit of a gate array and a CPU. That is, the main controller is provided with a sector signal generator for generating the sector signal SP by using a signal read from the servo area by means of the head 101. The HDC 2 switches the read gate RG ON in synchronization with inputting of the sector signal SP when data reproducing processing is started.
With the read gate RG switched ON, as shown in FIGS. 20D and 20E, the read PLL 12 starts the phase acquisition operation and the AGC 8 starts an operation of controlling a gain of the VGA 3 so as to make stable an amplitude of the read signal RS in a high-speed follow-up mode (time Tag). The synch byte detection circuit 7 starts searching of a synch byte area (SB) (time Tss).
The ENDEC 10 outputs, as shown in FIGS. 21A and 21B, the NRZ data to the HDC 2 during the period of switching ON of the read gate RG to switching OFF. The HDC 2 switches the read gate RG OFF after recognizing ECC (error checking and correction) data. In FIG. 21C, "RC" is a timing chart indicating a state of controlling performed by a read lock RC output from the read PLL 12. "W" during the OFF period of the read gate RG (T6 and T7) means that the read PLL 12 is locked in a write clock pulse WC from the write clock generator 11.
The clock switching circuit 13 changes, when the read gate RG is switched OFF, a switch to an output side of the write clock generation circuit 11. When the read gate RG is ON, the clock switching circuit 13 changes the switch to an output side of the PR equalizer 6 so as to supply a synchronous clock in the VFO area of the read signal RS to the read PLL 12. "D" shown in FIG. 21C means digital data output from the A/D converter 5 with the read clock RC as a sample clock while the read gate RG is ON.
As mentioned above, the HDC 2 switches the read gate RG OFF after recognizing the ECC data. This ECC data is first input to the read channel 200 and output to the HDC 2 after a passage of proper delaying time. This is caused by circuit delaying of the viterbi decoder 9 or the ENDEC 10.
In particular, in the read channel of the PRML system, the NRZ decoder of the viterbi decoder 9 or the ENDEC 10 is constructed by a high-speed logic circuit, and in order to reduce power consumption an operational speed of the decoder is reduced by executing bit interleave processing and byte interleave processing in parallel.
Also, in the read channel of the high-speed PRML system, a pass-memory length of the viterbi decoder is made long structurally because of an increase in the number of taps for FIR (finite impulse response) filters (digital filter) constituting the digital system PR equalizer and thus circuit delaying time is further increased.
In the read channel having such a large decoder circuit delay, in particular when data are continuously reproduced from the adjacent data sectors, a synch byte detection error is generated and this will most likely cause a data reproducing error.
As a specific example, as shown in FIG. 20B, when the read gate RG is switched OFF to the previous data sector and this is switched ON to the next data sector, the HDC 2 switches the read gate RG ON to the next data sector after recognizing the ECC data of the previous data sector delayed equivalent to circuit delaying of the decoder. Therefore, the synch byte detection circuit 7 cannot search a synch byte area (SB) of the next data sector and this may cause a synch byte error (FIG. 20F). When the synch byte error occurs, as shown in FIG. 21C, a locking operation of the read PLL is not allowed and this will cause error data in the NRZ data.
In order to solve these problems, as shown in FIG. 22A, enlarging of a gap area of the data sector (GAP) 90 may be considered. In such a sector format, as shown in FIG. 22F, even when data are continuously reproduced, a synch byte area (SB) of the next data sector can be surely searched. Also, as shown in FIG. 23B, accurate NRZ data can be output. However, if the gap area (GAP) is made large, this will cause reduction in data format efficiency and a data recording density.